Method for clamping a semiconductor region at or near ground

ABSTRACT

A clamping circuit clamps a voltage received by an n-type semiconductor region without using a Schottky transistor. The clamping circuit includes a current mirror as well as first and second bipolar transistors. The current mirror receives a first current and supplies a second current in response. The first current is received by the first bipolar transistor, and the second current is received by the second bipolar transistor. The difference between the base-emitter junction voltages of the first and second bipolar transistors, in part, defines the voltage at which the n-type region is clamped. To start-up the circuit properly, current is withdrawn from the base/gate terminals of the transistors disposed in the current mirror. The circuit optionally includes a pair of cross-coupled transistors to reduce the output impedance and improve the power supply rejection ratio.

CROSS-REFERENCES TO RELATED APPLICATIONS

The present application claims benefit under 35 USC 119(e) of U.S. provisional Application No. 60/908,922, filed Mar. 29, 2007, entitled “Method For Clamping A Semiconductor Region At Or Near Ground”, the content of which is incorporated herein by reference in its entirety.

BACKGROUND OF THE INVENTION

The present invention relates to semiconductor integrated circuits, and more particularly to a circuit for clamping the voltage received by an n-type region formed in a semiconductor substrate.

One conventional technique for ensuring that the voltage applied to an n-type semiconductor region does not fall significantly below the ground potential, is to place a Schottky diode between the n-type region and the ground, and further, to place a current limiting resistor between the n-type region and the node that may pull the n-type region below the ground potential, as shown in FIG. 1. As node 16 is pulled below the ground potential, Schottky diode 12 is forward biased thus maintaining n-type region 10 clamped at a forward Schottky diode voltage below the ground potential.

One disadvantage of the clamping circuit shown in FIG. 1 is that Schottky diode 12, which is a metal-semiconductor junction may not be available for use. Second, if the Schottky diode has a relatively high series resistance and/or a high forward voltage, n-type region 10 may be clamped at a voltage sufficiently below the ground potential as to cause an associated parasitic lateral NPN transistor to turn on.

SUMMARY OF THE INVENTION

In accordance with the present invention, a clamping circuit clamps a voltage received by an n-type semiconductor region without using a Schottky transistor. In accordance with one embodiment, the clamping circuit includes a current mirror as well as first and second bipolar transistors. The current mirror receives a first current and supplies a second current in response. The first current is received by the first bipolar transistor, and the second current is received by the second bipolar transistor. The difference between the base-emitter junction voltages of the first and second bipolar transistors defines the voltage at which the n-type region is clamped. To start-up the circuit properly, current is withdrawn from the base (gate) terminals of the transistors disposed in the current mirror.

In accordance with another embodiment, a clamping circuit includes a current mirror, as well as first, second, third and fourth bipolar transistors. The third and fourth bipolar transistors form a cross-coupled transistor pair. The current mirror receives a first current and supplies a second current in response. The first current is received by the first and third bipolar transistors. The second current is received by the second and fourth bipolar transistors. The emitter-base junction voltages of the first and second bipolar transistors together with the base-emitter junction voltages of the third and fourth transistors define the voltage at which the n-type region is clamped. A current source supplying a current to the first bipolar transistor ensures that the clamping circuit starts up properly.

In accordance with another embodiment, a clamping circuit includes a current mirror, as well as first, second, third and fourth bipolar transistors. The third and fourth bipolar transistors form a cross-coupled transistor pair. The current mirror receives a first current and supplies a second current in response. The first current is received by the first and third bipolar transistors. The second current is received by a fifth transistor coupled to the first and third transistor and adapted to develop a base-emitter voltage substantially similar to the base-emitter voltage of the first and third transistors. The emitter-base junction voltages of the first and second bipolar transistors together with the base-emitter junction voltages of the third and fourth transistors define the voltage at which the n-type region is clamped. To start-up the circuit properly, current is withdrawn from the base (gate) terminals of the transistors disposed in the current mirror.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic diagram of a circuit adapted to clamp the voltage applied to an n-type semiconductor region, as known in the prior art.

FIG. 2 is a schematic diagram of a circuit adapted to clamp the voltage applied to an n-type semiconductor region, in accordance with one exemplary embodiment of the present invention.

FIG. 3A is a cross-section of a substrate showing a number of different regions associated with the circuit of FIG. 2, in accordance with one exemplary embodiment of the present invention.

FIG. 3B is a cross-section of a substrate showing a number of different regions associated with the circuit of FIG. 2, in accordance with another exemplary embodiment of the present invention.

FIG. 4 is a schematic diagram of a circuit adapted to clamp the voltage applied to an n-type semiconductor region, in accordance with one exemplary embodiment of the present invention.

FIG. 5 is a schematic diagram of a circuit adapted to clamp the voltage applied to an n-type semiconductor region, in accordance with one exemplary embodiment of the present invention.

FIG. 6 is a schematic diagram of a circuit adapted to clamp the voltage applied to an n-type semiconductor region, in accordance with one exemplary embodiment of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

In accordance with the present invention, an n-type semiconductor region is clamped at or near the ground potential without the use of a Schottky transistor. Although the following description is provided with reference to bipolar transistors, it is understood that MOS transistors may also be used to clamp an n-type semiconductor region in accordance with the present invention.

FIG. 2 is a transistor schematic diagram of a clamping circuit 50 adapted to clamp n-type semiconductor region 20 to a known voltage, in accordance with one exemplary embodiment of the present invention. Clamping circuit 50 is shown as including bipolar PNP transistors 22, 24, as well as bipolar NPN transistors 26, 28. PNP transistors 22 and 24 have the same base-emitter voltage and form a current mirror. Accordingly, current I₂₈ supplied by the current mirror is proportional or substantially equal to current I₂₆ received by the current mirror. Current limiting resistor 30 is disposed between the emitter terminal of transistor 26 and node 55 to which voltage V_(Test) is applied.

As voltage V_(Test) is pulled below the ground potential, transistor 32 begins to draw a relatively small amount of current from the base terminals of transistors 22 and 24, thereby causing clamping circuit 50 to start up properly. Because transistors 22 and 24 form a current mirror, the ratio of the collector current I₂₆ of transistor 26 to the collector current I₂₈ of transistor 28 is determined by the relative base-emitter areas of transistors 22 and 24.

Assume that the ratio of the base-emitter area of transistor 22 to transistor 24 is X. The voltage received by n-type region 20 with respect to the ground potential is defined by the difference between the base-emitter regions of transistors 26 and 28, namely VBE₂₈-VBE₂₆, where VBE₂₈ is the voltage across the base-emitter terminals of transistor 28 and VBE₂₆ is the voltage across the base-emitter terminals of transistor 26. Voltages VBE₂₆ and VBE₂₈ are related to currents I₂₆ and I₂₈ according to the following:

VBE ₂₈=(kT/q)*ln(I ₂₈ /I ₂₈)  (1)

VBE ₂₆=(kT/q)*ln(I ₂₆ /I ₂₆)  (2)

VBE ₂₈ −VBE ₂₆=(kT/q)*ln(I ₂₈ /I _(s28))−(kT/q)*ln(I ₂₆ /I _(s26))  (3)

where k is Boltzmann's constant (1.38×10⁻²³), T is the temperature in Kelvin, q is the electron's charge, I_(s26) and I_(s28) are constant values, respectively defined by the transfer characteristics of transistors 26 and 28 in the forward-active region.

Equation (3) may be simplified as:

VBE ₂₈ −VBE ₂₆=(kT/q)*ln(X*(I _(s26) /I _(s28)))  (4)

where I_(s26)/I_(s28) is the ratio of the base-emitter areas of transistors 26 and 28.

Assume the area of transistor 28 is Y times the area of transistor 26. Since I₂₈=X*I₂₆, the voltage of region 20 is defined by the following:

VBE ₂₈ −VBE ₂₆=(kT/q)*ln(X/Y)  (5)

Since (kT/q) is constant for any given temperature, from equation (5) it is seen that the voltage of region 20 may be controlled by selecting the ratio of X and Y. For example, if X and Y are both selected to be equal to 1, the voltage of n-type region 20 with respect to ground may be set to zero. If Y is selected to be twice as large as X, the voltage of n-type region 20 with respect to ground may be set to (−18 mV) at room temperature. It is often desirable to set the clamp point slightly below ground to prevent the circuit from conducting current during a shutdown state.

Current limiting resistor 30 limits the amount of current I₂₆ flowing through transistors 26 and 24, according to the following:

I ₂₆=((voltage of clamped region 20)−V _(test))/(R ₃₀)

where R₃₀ is the resistance of resistor 30; this resistance is typically selected to be sufficiently large to keep the currents flowing through transistors 22, 24, 26, and 28 relatively small in order to ensure proper operation.

PNP transistors 22 and 24 may be either lateral or vertical PNP transistors. Transistors 26, 28 and 32 may be either lateral or vertical NPN transistors. Transistor 32 may be a parasitic NPN transistor that when selected to be a lateral NPN transistor may be formed by placing n-type region 20 in close proximity of transistors 22, 24, or alternatively by placing an n-type moat around n-type region 20 and connecting the moat to the bases of transistors 22 and 24.

Concurrent references are made below to FIGS. 2 and 3A. FIG. 3A is a cross-sectional view of a semiconductor substrate 40 having formed therein a number of different regions associated with clamp circuit 50 of FIG. 2, in accordance with one exemplary embodiment of the present invention. N-type region 20 is assumed to be an epitaxial region that is clamped in accordance with one embodiment of the present invention. In the embodiment shown in FIG. 3A, it is assumed that transistors 22 and 24 (see FIG. 2) are not in the vicinity of n-type region 20. N-type region 56 and n+ region 46 is connected to the base terminals of transistors 22, 24 via a metal layer (not shown) and form the collector region of transistor 32 of FIG. 2. P-type substrate region 40 and n-type region 20 respectively form the base and emitter regions of transistor 32 of FIG. 2.

Concurrent references are made below to FIGS. 2 and 3B. FIG. 3B is a cross-sectional view of a semiconductor substrate 70 having formed therein a number of different regions associated with clamp circuit 50 of FIG. 2, in accordance with another exemplary embodiment of the present invention. In this embodiment, n-type region 56 and n+ region 54 together are assumed to form the base region of transistor 24 (or 22), as well as the collector terminal of transistor 32. P-type substrate region 40 and n-type region 20 respectively form the base and emitter regions of transistor 32 of FIG. 2.

FIG. 4 is a transistor schematic diagram of a clamping circuit 150 adapted to clamp n-type semiconductor region 20 to a known voltage, in accordance with another exemplary embodiment of the present invention. Clamping circuit 150 is similar to clamping circuit 50 except that in clamping circuit 150, transistors 122 and 124 are PMOS transistors. The ratio of the channel-width to channel length of transistors 122, 124, in addition to the ratio of the emitter-base areas of transistors 26 and 28 collectively define the voltage at which n-type region 20 is clamped.

FIG. 5 is a transistor schematic diagram of a clamping circuit 100 adapted to clamp n-region 40 to a known voltage, in accordance with another exemplary embodiment of the present invention. Clamping circuit 100 is shown as including bipolar PNP transistors 142, 144, as well as bipolar NPN transistors 146, 148, 150 and 152. PNP transistors 142 and 144 have the same base-emitter voltages and form a current mirror, accordingly, current I₁ supplied by this current mirror is proportional or substantially equal to current I₂ received by this current mirror. Current I₁ is shown as also flowing through transistors 146 and 148. Likewise, current I₂ is shown as also flowing through transistors 150 and 152. Current limiting resistor 156 is disposed between the emitter terminal of transistor 150 and node 55 to which voltage V_(Test) is applied.

Current I_(trickle) supplied by current source 54 is used to properly start up clamping circuit 150. As described above, transistors 142 and 144 form a current mirror, thus setting the currents that flow through transistors 146, 148, on the one hand, and transistors 150 and 152, on the other, at a predetermined ratio. The voltage of the clamped n-type region 40 relative to the ground is defined by the following:

VBE₁₅₀+VBE₁₄₆−VBE₁₅₂−VBE₁₄₈  (6)

where VBE₁₅₀, VBE₁₄₆, VBE₁₅₂, and VBE₁₄₈ represent the base-emitter voltages of transistors 150, 146, 152 and 148 respectively.

By selecting the ratio of the base-emitter areas of the various transistors shown in FIG. 5, the voltage at which n-type region 40 is clamped, is set to a desired value. N-type region 40 is clamped in accordance with the following expression:

$\begin{matrix} {\left( \frac{KT}{q} \right){\ln \left( \frac{I_{s\; 152} \times I_{s\; 148}}{I_{s\; 148} \times I_{s\; 150}} \right)}} & (7) \end{matrix}$

where I_(s152), I_(s148), I_(s146), and I_(s150) are values respectively defined by the transfer characteristics of transistors 152, 148, 146 and 150 in the forward-active region. Cross-coupled transistors 148 and 150 reduce the output impedance and improve the power supply rejection ratio. In some embodiments, PMOS transistors may be used in place of PNP transistors 142 144. The cross-coupled transistors 148 and 150 cancel collector current mismatches between transistors 142, 152 and 150 disposed in current leg 155, and transistors 144, 146 and 148 disposed in current leg 145. If the supply voltage V_(CC) rises, early voltage effects cause a shift in the current ratio of transistors 142 and 144. The cross-coupling of transistors 148 and 150 cancels out such a current shift, thereby improving the power supply rejection ratio. As n-type region 40 is pulled further below the ground potential, the level of currents flowing through the base terminals of transistors 142 and 144 increases. The cross-coupling of transistors 148 and 150 cancels out any shift that would otherwise occur in the collector currents of transistors 142 and 144 as a result of increases in the base currents of these two transistors.

FIG. 6 is a transistor schematic diagram of a clamping circuit 200 adapted to clamp n-region 80 to a known voltage, in accordance with another exemplary embodiment of the present invention. Clamping circuit 200 is shown as including, in part, bipolar PNP transistors 270, 272, as well as bipolar NPN transistors 268, 266, 264, 260 and 262. Transistor 272, also disposed in clamping circuit 200, may be a parasitic NPN transistor used to start up circuit 200. The following description is provided with reference to setting the clamp voltage of n-region 80 to nearly 0 volts, i.e., the ground potential. It is understood, however, that the clamp voltage of n-region 80 may be selectively set to any other desired value by varying the ratio of the emitter-base areas of the various transistors shown in circuit 200 in a manner generally similar to that described above with respect to FIG. 2.

Current limiting resistor 276 is disposed between the emitter terminal of transistor 262 and node 55 to which voltage V_(Test) is applied. As voltage V_(Test) is pulled below the ground potential, transistor 272 is turned on, thereby pulling a relatively small amount of current out from the base terminals of transistors 270 and 274, in turn, ensuring that circuit 200 starts up properly.

Transistors 270 and 274 form a current mirror, therefore assuming transistors 270 and 274 have similar base-emitter areas, current I₁ is substantially equal to current I₂. Therefore, assuming that the base currents are negligible, the collector currents of transistors 266 and 268 are substantially equal. Consequently, the base-emitter voltage of transistor 268, namely VBE₂₆₈, is substantially equal to the base-emitter voltage of transistor 266, namely VBE₂₆₆. Since the emitter terminals of both transistors 268 and 266 receive the ground potential, the voltage at node N1 is substantially equal to the voltage at node N2.

Because the emitter voltages of transistors 260 and 264 are substantially the same and the base terminals of these two transistors are coupled to one another, current I₂ flowing through transistor 264 is substantially equal to current I₃ flowing through transistor 260. Hence, neglecting base currents, because current I₂ is equal to current I₃, the base-emitter voltage of transistor 266, i.e., VBE₂₆₆ is substantially equal to the base-emitter voltage of transistor 262, i.e., VBE₂₆₂. Likewise, the base-emitter voltage of transistor 264, i.e., VBE₂₆₄ is substantially equal to the base-emitter voltage of transistor 266. Accordingly:

VBE₂₆₈=VBE₂₆₆=VBE₂₆₄=VBE₂₆₀=VBE₂₆₂  (8)

As seen from FIG. 5, the voltage at n-type region 80 is defined by the following expression:

VBE₂₆₆+VBE₂₆₀−VBE₂₆₄−VBE₂₆₂  (9)

Since the base-emitter voltages of transistors 266, 260, 264 and 262 are substantially the same, as shown in expression (8), the voltage at n-type region 80 is nearly equal to zero. As described above, by varying the ratio of the emitter-base areas of the transistors shown in circuit 100, the voltage at which n-type region 80 is clamped, may be selectively set to any other desired value. N-type region 80 is clamped in accordance with the following expression:

$\begin{matrix} {\left( \frac{KT}{q} \right){\ln \left( \frac{I_{s\; 264} \times I_{s\; 262}}{I_{s\; 266} \times I_{s\; 260}} \right)}} & (10) \end{matrix}$

where I_(s265), I_(s262), I_(s266), and I_(s260) are values respectively defined by the transfer characteristics of transistors 264, 262, 266 and 260 in the forward-active region

The above embodiments of the present invention are illustrative and not limiting. Various alternatives and equivalents are possible. The invention is not limited by the type of transistors or integrated circuits in which the present invention may be disposed. Nor is the disclosure limited to any specific type of process technology, e.g., CMOS, Bipolar, or BICMOS that may be used to manufacture the present disclosure. Other additions, subtractions or modifications are obvious in view of the present disclosure and are intended to fall within the scope of the appended claims. 

1. A circuit adapted to control a clamping voltage of a semiconductor region formed in a semiconductor substrate, the circuit comprising: a current mirror receiving a first current and supplying a second current in response; a first transistor adapted to generate a first voltage in accordance with the first current; and a second transistor adapted to generate a second voltage in accordance with the second current; wherein said clamping voltage is defined by a difference of said first and second voltages.
 2. The circuit of claim 1 wherein said first and second transistors are bipolar transistors, and said first and second voltages are base-emitter voltages.
 3. The circuit of claim 1 wherein said first and second transistors are MOS transistors, and said first and second voltages are gate-source voltages.
 4. The circuit of claim 2 wherein said first bipolar transistor is a NPN transistor having an emitter terminal coupled to the semiconductor region, and wherein said second bipolar transistor is an NPN transistor having an emitter terminal coupled to a ground terminal.
 5. The circuit of claim 4 wherein said current mirror comprises: a third bipolar transistor having an emitter terminal coupled to a first supply voltage, and a collector terminal coupled to the collector terminal of the first NPN transistor; and a fourth bipolar transistor having an emitter terminal coupled to the first supply voltage, a collector terminal coupled to the collector terminal of the second NPN transistor, and a base terminal coupled to the base terminal of the third bipolar transistor.
 6. The circuit of claim 4 wherein said current mirror comprises: a first MOS transistor having a source terminal coupled to a first supply voltage, and a drain terminal coupled to the collector terminal of the first NPN transistor; and a second MOS transistor having a source terminal coupled to the first supply voltage, a drain terminal coupled to the collector terminal of the second NPN transistor, and a gate terminal coupled to the gate terminal of the third bipolar transistor.
 7. The circuit of claim 5 further comprising: a fifth bipolar transistor having a base terminal coupled to the emitter terminal of the second transistor, an emitter terminal coupled to the semiconductor region and a collector terminal coupled to the base terminal of the third transistor.
 8. The circuit of claim 7 further comprising: a resistive element coupled to the semiconductor region.
 9. A method of controlling a clamping voltage of a semiconductor region formed in a semiconductor substrate, the method comprising: causing a first voltage to be supplied in accordance with a first current; causing a second voltage to be supplied in accordance with a second current; and applying a voltage defined by a difference of said first and second voltages between the semiconductor region and a ground terminal.
 10. The method of claim 9 wherein said first voltage is caused to be supplied across a first base-emitter junction formed in a first bipolar transistor, and wherein said second voltage is caused to be supplied across a second base-emitter junction formed in a second bipolar transistor.
 11. The method of claim 9 wherein said first voltage is caused to be supplied across a first gate-to-source junction of a first MOS transistor, and wherein said second voltage is caused to be supplied across a gate-to-source junction of a second bipolar transistor.
 12. The method of claim 10 wherein said first current is supplied by a third bipolar transistor and wherein said second current is supplied by a fourth bipolar transistor, the method further comprising: drawing current from base terminals of the first and second bipolar transistors during a start-up phase.
 13. The method of claim 10 wherein said first current is supplied by a first MOS transistor and wherein said second current is supplied by a second MOS transistor, the method further comprising: drawing current from gate terminals of the first and second MOS transistors during a start-up phase.
 14. A circuit adapted to control a clamping voltage of a semiconductor region formed in a semiconductor substrate, the circuit comprising: a current mirror receiving a first current and supplying a second current in response; a first transistor adapted to generate a first voltage in accordance with the first current; a second transistor adapted to generate a second voltage in accordance with the second current; and a cross-coupled transistor pair having disposed therein a third transistor adapted to generate a third voltage in accordance with the first current and a fourth transistor adapted to generate a fourth voltage in accordance with the second current; wherein said clamping voltage is defined by a difference of a sum of said first and fourth voltages and a sum of said second and third voltages.
 15. The circuit of claim 14 wherein said first, second, third and fourth transistors are bipolar transistors, and said first, second, third and fourth voltages are base-emitter voltages.
 16. The circuit of claim 14 wherein said first, second, third and fourth transistors are MOS transistor, and said first, second, third and fourth voltages are gate-to-source voltages.
 17. The circuit of claim 14 wherein said first, second, third and fourth transistors are bipolar NPN transistors, wherein an emitter terminal of the first transistor is coupled to a base terminal of the fourth transistor and to a collector terminal of the third transistor, wherein an emitter terminal of the second transistor is coupled to a base terminal of the third transistor and to a collector terminal of the fourth transistor, wherein an emitter terminal of the fourth transistor is coupled to the semiconductor region and wherein an emitter terminal of the third transistor is coupled to the ground terminal.
 18. The circuit of claim 17 wherein said current mirror comprises: a fifth bipolar transistor having an emitter terminal coupled to a first supply voltage, a collector terminal coupled to collector and base terminals of the first bipolar transistor; and a sixth bipolar transistor having an emitter terminal coupled to the first supply voltage, a collector terminal coupled to the collector terminal of the second bipolar transistor, and a base terminal coupled to the base terminal of the fifth bipolar transistor and to a collector terminal of the second bipolar transistor.
 19. The circuit of claim 18 further comprising: a current source adapted to supply a current to collector terminals of the first and fifth bipolar transistors.
 20. The circuit of claim 19 further comprising: a resistive element coupled to the semiconductor region.
 21. A method of controlling a clamping voltage of a semiconductor region formed in a semiconductor substrate, the method comprising: causing first and second voltages to be supplied in accordance with a first current; causing third and fourth voltages to be supplied in accordance with a second current; generating a fifth voltage defined by a difference of a sum of said first and fourth voltages and a sum of said second and third voltages; and applying the fifth voltage between the semiconductor region and a ground terminal.
 22. The method of claim 21 wherein said first and second, third and fourth voltages are base-emitter voltages of first, second, third and fourth bipolar transistors respectively.
 23. The method of claim 21 wherein said first, second, third and fourth voltages are gate-to-source voltages of first, second, third and fourth MOS transistors respectively.
 24. The method of claim 21 wherein said first current is supplied by a third bipolar transistor and wherein said second current is supplied by a fourth bipolar transistor, the method further comprising: supplying a current to a terminal of the third bipolar transistor during a start-up phase.
 25. The method of claim 21 wherein said first current is supplied by a first MOS transistor and wherein said second current is supplied by a second MOS transistor, the method further comprising: supplying a current to a terminal of the first MOS transistor during a start-up phase.
 26. A circuit adapted to control a clamping voltage of a semiconductor region formed in a semiconductor substrate, the circuit comprising: a first transistor adapted to supply a first voltage in accordance with a first current; a second transistor adapted to supply a second voltage in accordance with a second current; and a cross-coupled transistor pair having a third transistor adapted to supply a third voltage in accordance with the first current, and a fourth transistor adapted to supply a fourth voltage in accordance with the second current; wherein said clamping voltage is defined by a difference of a sum of the second and third voltages and a sum of said first and fourth voltages.
 27. The circuit of claim 26 wherein said first, second, third and fourth voltages are base-emitter voltages of first, second, third and fourth bipolar transistors.
 28. The circuit of claim 26 wherein said first, second, third and fourth voltages are gate-to-source voltages of first, second, third and fourth MOS transistors.
 29. The circuit of claim 27 wherein said first, second, third and fourth transistors are bipolar NPN transistors, wherein an emitter terminal of the first transistor is coupled to the base terminal of the fourth transistor and to a collector terminal of the third transistor, wherein an emitter terminal of the second transistor is coupled to the base terminal of the third transistor and to a collector terminal of the fourth transistor, wherein an emitter terminal of the fourth transistor is coupled to the semiconductor region and wherein an emitter terminal of the third transistor is coupled to a ground terminal.
 30. The circuit of claim 29 wherein said circuit further comprises: a fifth transistor having a first terminal coupled to a first supply voltage, and a second terminal coupled to the collector and base terminals of the first bipolar NPN transistor; a sixth transistor having a first terminal coupled to the first supply voltage, and second and third terminals coupled to a third terminal of the fifth transistor; and a seventh transistor having a first terminal coupled to the second terminal of the sixth transistor, a second terminal coupled to the base terminal of the fourth transistor, and a third terminal coupled to the ground terminal.
 31. The circuit of claim 30 wherein said fifth and sixth transistors are bipolar PNP transistors.
 32. The circuit of claim 30 wherein said fifth and sixth transistors are PMOS transistors.
 33. The circuit of claim 31 wherein said circuit further comprises: an eight bipolar NPN transistor having a collector terminal coupled to the collector terminal of the seventh transistor, a base terminal coupled to the ground terminal, and an emitter terminal coupled to the semiconductor region.
 34. A method of controlling a clamping voltage of a semiconductor region formed in a semiconductor substrate, the method comprising: causing first and second voltages to be supplied in accordance with a first current; causing third and fourth voltages to be supplied in accordance with a second current; developing a fifth voltage defined by a difference of a sum of said second and third voltages and a sum of said first and fourth voltages; applying the fifth developed voltage across the semiconductor region and a ground terminal; and withdrawing current from said first and second transistors during a start-up phase.
 35. The method of claim 34 wherein said first and second voltages are base-emitter voltages of first and second bipolar transistors respectively.
 36. The method of claim 34 wherein said first and second voltages are gate-to-source voltages of first and second MOS transistors respectively.
 37. A circuit adapted to control a clamping voltage of a semiconductor region formed in a semiconductor substrate, the circuit comprising: a first bipolar transistor having an emitter terminal coupled to the semiconductor region, wherein a biasing voltage applied to the first transistor is in part proportional to a current flowing through the first transistor.
 38. The circuit of claim 37 further comprising: a second bipolar transistor flowing a current that is proportional to the current flowing through the first transistor. 